Power Consumption Versus Configuration SEUs in Xilinx Virtex-5 FPGAs

SEUs in the configuration memory are the major cause of faults in SRAM-based FPGAs exposed to radiation. Most of the research about this topic focuses on studying the mechanism of random changes in the FPGA resources (logic blocks, flip-flops, IO, and interconnection network) for their impact on the overall device reliability and fault analysis, while much less effort has been spent in evaluating the effects of SEUs on power consumption. In this paper, we present a detailed analysis of the power consumption of a Xilinx Virtex 5 LX50T on the CORE, AUX, MGT and IO domains during irradiation with 62-MeV proton beams. The tests have been performed at the Superconductive Cyclotron of the LNS-INFN facility (Catania, Italy). Changes in power consumption (most notably in the logic core) are experienced. We present an analysis of the current trends and the results of fault injection tests, on the programmable routing resources, aimed at confirming or excluding possible fault mechanisms for the SEU-induced current variations.