A Capacitance-Coupled Bit Line Cell

A 38-/spl mu/m/sup 2/ dynamic random-access memory (dRAM) cell with a capacitance-coupled bit line (CCB) approach is described. This cell enables a storage capacitor area 2-2.5 times larger than double polysilicon-type cells, or half the cell area with the same design rules. Memory operation with this cell is explained and the bit line stray capacitance is analyzed using a two-dimensional numerical calculation method. The cell output voltage is compared with those of other cells, taking the capacitance between bit lines into account. An experimental 256K dRAM was built for testing, and operated successfully.

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