Constrained synthesis and optimization of digital integrated circuits from behavioral specifications

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with the increasing complexity of digital hardware design. This dissertation addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. Previous synthesis approaches addressed processor and digital signal processing designs. These designs usually consist of computations that are performed within a certain time frame with little or no coordination with other components in the system. In contrast, Application Specific Integrated Circuit (ASIC) designs perform computations that are specific to a particular user application. ASIC designs are typified by communication and control-dominated designs with complicated handshaking and timing requirements. An example of an ASIC is a network controller that facilitates communication activities of a computer system on a shared network. This dissertation focuses on constructing a computer-aided synthesis system targeted towards synchronous ASIC designs. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of this research is to develop a hardware model incorporating these requirements and to develop synthesis algorithms that operate on this hardware model. The contributions of this dissertation address both theory and implementation of algorithms for hardware synthesis. The following novel synthesis algorithms have been developed: relative scheduling, a scheduling formulation that supports external synchronizations and timing constraints; constrained conflict resolution, a method to resolve resource conflicts under timing constraints; and relative control synthesis, a control generation approach for relative scheduling. In addition, a hardware description language called HardwareC was developed as the input to Hercules and Hebe. They are the system implementation of algorithms developed in this research and have been applied to the synthesis of benchmark examples and chip designs at Stanford University.