In-tier diagnosis of power domains in 3D TSV ICs

Power and substrate domains are strategically isolated or unified in heterogeneous 3D integration. In-tier probing circuitry provides accessibility to power delivery and substrate networks in a deep tier of a 3D chip stack and capability of diagnosing intra/inter tier coupling. A two-tier demonstrator was successfully tested in a 130 nm CMOS, 3D-SIC Cu TSV technology.

[1]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.

[2]  A. Jourdain,et al.  3D stacked IC demonstration using a through Silicon Via First approach , 2008, 2008 IEEE International Electron Devices Meeting.

[3]  M. Facchini,et al.  Stackable memory of 3D chip integration for mobile applications , 2008, 2008 IEEE International Electron Devices Meeting.

[4]  Eric Beyne,et al.  Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping , 2009, 2009 IEEE International Conference on 3D System Integration.

[5]  Takushi Hashida,et al.  An on-chip waveform capturing technique pursuing minimum cost of integration , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.