Test Pattern Compression Based on Pattern Overlapping

This paper describes a test data compression method based on pattern overlapping. We report here improvements that have been done on the test pattern compaction and compression algorithm called COMPAS. This algorithm reorders and compresses test patterns previously generated in an ATPG in such a way that they are well suited for decompression by the scan chains in the embedded tester cores. It compresses the test patterns by overlapping patterns originally generated by an ATPG. The problem of the COMPAS algorithm is that it has to manipulate with enormous amount of data when compressing test sets of large circuits and the CPU time grows rapidly with the growing number of test vectors. These disadvantages were solved by using a test vector initial encoding by sparse vectors and by using a dynamic structure for storing the pre-calculated parameters of candidate vectors to be used in the near future algorithm loops for overlapping with the actual scan chain content. This arrangement allows the algorithm to skip unnecessary computations. The improvements cause that the CPU time grows approximately linearly with the size of the tested circuit. The improved algorithm is also capable to compress data generated by concurrently working ATPG processes.

[1]  Hans-Joachim Wunderlich,et al.  RESPIN++ - deterministic embedded test , 2002, Proceedings The Seventh IEEE European Test Workshop.

[2]  Huaguo Liang,et al.  A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters , 2001, J. Electron. Test..

[3]  H. K. Lee,et al.  HOPE: an efficient parallel fault simulator , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[4]  Alex Orailoglu,et al.  Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[5]  Ondrej Novák,et al.  Test pattern decompression using a scan chain , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[6]  Ondrej Novák,et al.  COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits , 2005, EDCC.

[7]  Nilanjan Mukherjee,et al.  Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Wilfried Daehn,et al.  Hardware Test Pattern Generation for Built-In Testing , 1981, International Test Conference.

[9]  Wenjing Rao,et al.  Virtual compression through test vector stitching for scan based designs , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[10]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[11]  Nur A. Touba,et al.  Scan vector compression/decompression using statistical coding , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[12]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[13]  Hans-Joachim Wunderlich,et al.  Reusing Scan Chains for Test Pattern Decompression , 2002, J. Electron. Test..

[14]  David M. Wu,et al.  An optimized DFT and test pattern generation strategy for an Intel high performance microprocessor , 2004, 2004 International Conferce on Test.

[15]  Chauchin Su,et al.  A serial scan test vector compression methodology , 1993, Proceedings of IEEE International Test Conference - (ITC).

[16]  Gundolf Kiefer,et al.  Circuit partitioning for efficient logic BIST synthesis , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[17]  Sarita Thakar,et al.  On the generation of test patterns for combinational circuits , 1993 .

[18]  Yervant Zorian,et al.  Towards a standard for embedded core test: an example , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[19]  Brion L. Keller,et al.  OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[20]  Janak H. Patel,et al.  Reconfiguration technique for reducing test time and test data volume in Illinois Scan Architecture based designs , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[21]  Nur A. Touba,et al.  Reducing test data volume using LFSR reseeding with seed compression , 2002, Proceedings. International Test Conference.

[22]  Lei Li,et al.  Test Data Compression Using Dictionaries with Fixed-Length Indices , 2003 .

[23]  Christos A. Papachristou,et al.  Multiscan-based test compression and hardware decompression using LZ77 , 2002, Proceedings. International Test Conference.

[24]  James H. Aylor,et al.  An analysis of fault partitioned parallel test generation , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Jiri Jenícek,et al.  Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[26]  Lei Li,et al.  Test set embedding for deterministic BIST using a reconfigurable interconnection network , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  Krishnendu Chakrabarty,et al.  Frequency-Directed Run-Length (FDR) Codes , 2002 .