A 60 GHz Injection-Locked Frequency Tripler With Spur Suppression

A 60 GHz injection-locked frequency tripler is designed to improve spectral purity with spur suppression of the fundamental and the even-order harmonics. Several circuit designs are utilized in the harmonic current injection circuit to maximize the third-order harmonic and minimize the undesired harmonic current outputs, including notch filters and a capacitive cross-coupled transistor pair. With the input signal of 0.5 dBm at 19.7 GHz, the harmonic rejection ratios of the fundamental, and the second-order achieve 31.3 dBc, and 45.8 dBc, respectively. Implemented in 0.13 m CMOS technology, the core circuit consumes power of 9.96 mW with 1.2 V supply voltage. The entire die occupies an area of 985 × 866 μm2.

[1]  J.R. Long,et al.  A 56–65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[2]  B. Razavi A study of injection locking and pulling in oscillators , 2004, IEEE Journal of Solid-State Circuits.

[3]  Yu Wang,et al.  Simultaneous sub-harmonic injection-locked mm-wave frequency generators for multi-band communications in CMOS , 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

[4]  Chien-Nan Kuo,et al.  A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 µm CMOS , 2009, IEEE J. Solid State Circuits.

[5]  G.R. Branner,et al.  Design and optimization of large conversion gain active microwave frequency triplers , 2005, IEEE Microwave and Wireless Components Letters.

[6]  Chung-Yu Wu,et al.  Design and Analysis of CMOS Subharmonic Injection-Locked Frequency Triplers , 2008, IEEE Transactions on Microwave Theory and Techniques.