Automated Analysis of Virtual Prototypes at Electronic System Level

The exponential increase in functionality of System-on-Chips (SoCs) and reduced Time-to-Market (TTM) requirements have significantly altered the typical design and verification flow. Virtual Prototyping (VP) at the Electronic System Level (ESL) using SystemC and its Transaction Level Modeling (TLM) framework is an industry-accepted solution. VP design exploration, review, debugging, and integration of ever changing functional requirements can be made faster with the help of design understanding and visualization methods. Hence, in this paper, we propose a fully automated structural, and behavioral analysis approach for visualization of ESL VPs including TLM-2.0 VPs. At the heart of the analysis is a hybrid approach which uses static and dynamic methods to extract structural and behavioral information of the VP. Afterwards, the extracted information is translated into structural and graphical representations such as UML diagrams (specifying TLM-2.0 transactions' protocols), and XML format (describing designs' structure). Experimental results including a real-world VP shows the effectiveness of our approach.

[1]  Rolf Drechsler,et al.  Efficient Automatic Visualization of SystemC Designs , 2003, FDL.

[2]  Hiren D. Patel,et al.  Systemc-clang: An open-source framework for analyzing mixed-abstraction SystemC models , 2013, Proceedings of the 2013 Forum on specification and Design Languages (FDL).

[3]  René van Leuken,et al.  Extracting behavior and dynamically generated hierarchy from SystemC models , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[4]  Rolf Drechsler,et al.  AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration , 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

[5]  Rolf Drechsler,et al.  Overcoming limitations of the SystemC data introspection , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[6]  Rolf Drechsler,et al.  ParSyC: An Efficient SystemC Parser , 2004 .

[7]  Kevin Marquet,et al.  PinaVM: a systemC front-end based on an executable intermediate representation , 2010, EMSOFT '10.

[8]  Robert Wille,et al.  Data extraction from SystemC designs using debug symbols and the SystemC API , 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[9]  Rolf Drechsler,et al.  Automated Nonintrusive Analysis of Electronic System Level Designs , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Thomas Schuster,et al.  SoCRocket - A virtual platform for the European Space Agency's SoC development , 2014, 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

[11]  Wolfgang Klingauf,et al.  Design Structure Analysis and Transaction Recording in SystemC , 2006, FDL.

[12]  Tim Schmidt,et al.  Automatic Generation of Thread Communication Graphs from SystemC Source Code , 2016, SCOPES.