Impact of Epi-Si growth temperature on Ge-pFET performance

In this study, we report a direct comparison between two Epitaxial silicon processes: 500°C using SiH<inf>4</inf> and 350°C using Si<inf>3</inf>H<inf>8</inf>. Following four different metrics, we demonstrate that the reduction of Silicon growth temperature results into the introduction of negatively charged defects possibly located at the Si/SiO<inf>2</inf>interface. However, the Epi Si growth at 350°C with Si<inf>3</inf>H<inf>8</inf> remains beneficial compared to a growth performed at 500°C-SiH<inf>4</inf> especially when thin EOT Ge pFETs are targeted.