A fault tolerant hardware based file system manager for solid state mass memory

In this paper the hardware implementation of a file system manager for a fault tolerant Solid State Mass Memory (SSMM) is presented. A hardware implementation of the file system manager implies the following advantages: ad hoc fault tolerant design and graceful degradation capability. The former means developing special fault tolerant hardware for each file system basic function (read, write and delete). For each function different fault tolerant techniques have been applied by considering the impact of different faults on the architecture reliability. Also the area overhead introduced by the chosen fault tolerant technique has been evaluated. Graceful degradation is obtained in terms of data connection reconfiguration and reduced functionality set. We exploited the modularity of the design to implement a distributed file system by means of local handlers on each memory module connected to a dynamic routing module. The file system manager has been used in a SSMM oriented to satellite applications. An FPGA implementation for the complete SSMM has been obtained in order to evaluate the performances and reliability of the SSMM architecture and in particular of the file system manager.

[1]  Fritz Gliem,et al.  Fault-tolerance of spaceborne semiconductor mass memories , 1998, Digest of Papers. Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing (Cat. No.98CB36224).

[2]  Jean-Yves Le Gall,et al.  Design of a fault tolerant 100 Gbits solid-state mass memory for satellites , 1996, Proceedings of 14th VLSI Test Symposium.

[3]  Edward J. McCluskey,et al.  Parallel Signatur Analysis Design with Bounds on Aliasing , 1997, IEEE Trans. Computers.

[4]  Marco Ottavi,et al.  Development of a dynamic routing system for a fault tolerant solid state mass memory , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[5]  Gian Carlo Cardarilli,et al.  Fault-tolerant solid state mass memory for satellite applications , 1998, IMTC/98 Conference Proceedings. IEEE Instrumentation and Measurement Technology Conference. Where Instrumentation is Going (Cat. No.98CH36222).

[6]  Parag K. Lala,et al.  Fault tolerant and fault testable hardware design , 1985 .

[7]  Edward J. McCluskey,et al.  Concurrent Error Detection Using Watchdog Processors - A Survey , 1988, IEEE Trans. Computers.

[8]  John F. Meyer,et al.  On Evaluating the Performability of Degradable Computing Systems , 1980, IEEE Transactions on Computers.

[9]  Adelio Salsano,et al.  Design of fault-tolerant solid state mass memory , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).