Network-on-Chip

Introduction System-on-Chip Integration and Its Challenges SoC to Network-on-Chip: A Paradigm Shift Research Issues in NoC Development Existing NoC Examples Summary References Interconnection Networks in Network-on-Chip Introduction Network Topologies Switching Techniques Routing Strategies Flow Control Protocol Quality-of-Service Support NI Module Summary References Architecture Design of Network-on-Chip Introduction Switching Techniques and Packet Format Asynchronous FIFO Design GALS Style of Communication Wormhole Router Architecture Design VC Router Architecture Design Adaptive Router Architecture Design Summary References Evaluation of Network-on-Chip Architectures Evaluation Methodologies of NoC Traffic Modeling Selection of Channel Width and Flit Size Simulation Results and Analysis of MoT Network with WH Router Impact of FIFO Size and Placement in Energy and Performance of a Network Performance and Cost Comparison of MoT with Other NoC Structures Having WH Router under Self-Similar Traffic Simulation Results and Analysis of MoT Network with Virtual Channel Router Performance and Cost Comparison of MoT with Other NoC Structures Having VC Router Limitations of Tree-Based Topologies Summary References Application Mapping on Network-on-Chip Introduction Mapping Problem ILP Formulation Constructive Heuristics for Application Mapping Constructive Heuristics with Iterative Improvement Mapping Using Discrete PSO Summary References Low-Power Techniques for Network-on-Chip Introduction Standard Low-Power Methods for NoC Routers Standard Low-Power Methods for NoC Links System-Level Power Reduction Summary References Signal Integrity and Reliability of Network-on-Chip Introduction Sources of Faults in NoC Fabric Permanent Fault Controlling Techniques Transient Fault Controlling Techniques Unified Coding Framework Energy and Reliability Trade-Off in Coding Technique Summary References Testing of Network-on- Chip Architectures Introduction Testing Communication Fabric Testing Cores Summary References Application-Specific Network-on-Chip Synthesis Introduction ASNoC Synthesis Problem Literature Survey System-Level Floorplanning Custom Interconnection Topology and Route Generation ASNoC Synthesis with Flexible Router Placement Summary References Reconfigurable Network-on-Chip Design Introduction Literature Review Local Reconfiguration Approach Topology Reconfiguration Link Reconfiguration Summary References Three-Dimensional Integration of Network-on-Chip Introduction 3-D Integration: Pros and Cons Design and Evaluation of 3-D NoC Architecture Summary References Conclusions and Future Trends Conclusions Future Trends Comparison between Alternatives References Index

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