Heuristic Approach to Evaluate the Performance of Optimization Algorithms in VLSI Floor Planning for ASIC Design

A research on VLSI Floor planning’s physical layout is addressed using optimization methods to improve VLSI chip efficiency. VLSI floor planning is regarded as a non-polynomial issue. Calculations can solve such issues. Representation of floorplan is the basis of this process. The depictions of the floor plan demonstrate more effect on search space as well as the design complexity of the floor plan. This article aims at exploring various algorithms which add to the issue of managing alignment limitations such as excellent positioning, optimal region and brief run time. Many scientists are proposing and suggesting diverse heuristic algorithms and also distinct metaheuristic algorithms to solve the VLSI Floor plan issue. Simulated Annealing, tab search, ant colony optimization algorithm at last the genetic optimization algorithm are addressed in this article.

[1]  Jianli Chen,et al.  A hybrid genetic algorithm for VLSI floorplanning , 2010, 2010 IEEE International Conference on Intelligent Computing and Intelligent Systems.

[2]  Luca Maria Gambardella,et al.  Ant Algorithms for Discrete Optimization , 1999, Artificial Life.

[3]  P. Sivaranjani,et al.  Performance Analysis of VLSI Floor planning using Evolutionary Algorithm , 2013 .

[4]  T. Sravani,et al.  Review and analysis of promising technologies with respect to Fifth generation networks , 2014, 2014 First International Conference on Networks & Soft Computing (ICNSC2014).

[5]  Igor L. Markov,et al.  VLSI Physical Design - From Graph Partitioning to Timing Closure , 2011 .

[6]  Atsushi Takahashi,et al.  RRA-based multi-objective optimization to mitigate the worst cases of placement , 2011, 2011 9th IEEE International Conference on ASIC.

[7]  Kathryn A. Dowsland,et al.  Simulated Annealing , 1989, Encyclopedia of GIS.

[8]  Wiklom Teerapabkajorndet,et al.  Fault tolerant sensor placement optimization with minimum detection probability guaranteed , 2011, 2011 8th International Workshop on the Design of Reliable Communication Networks (DRCN).

[9]  Himadri Sekhar Dutta,et al.  Optimization of Floor-Planning using Genetic Algorithm , 2012 .

[10]  T. Stützle,et al.  A Review on the Ant Colony Optimization Metaheuristic: Basis, Models and New Trends , 2002 .

[11]  Tsung-Ying Sun,et al.  Floorplanning based on particle swarm optimization , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[12]  I. Hameem Shanavas,et al.  Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm , 2014 .

[13]  K Hari Kishore,et al.  An FPGA Implementation of On Chip UART Testing with BIST Techniques , 2016 .

[14]  Wali Md Abdullah,et al.  VLSI floorplanning design using clonal selection algorithm , 2013, 2013 International Conference on Informatics, Electronics and Vision (ICIEV).

[15]  S. Nazeer Hussain,et al.  Computational Optimization of Placement and Routing using Genetic Algorithm , 2016 .

[16]  Xi Chen,et al.  Regularity-constrained floorplanning for multi-core processors , 2014, Integr..

[17]  Hideki Asai,et al.  Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation , 2006, 2006 IEEE International Conference on Evolutionary Computation.