Radix-2n multiplier structures: a structured design methodology
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[1] Sun-Yuan Kung,et al. On supercomputing with systolic/wavefront array processors , 1984 .
[2] Keshab K. Parhi. A systematic approach for design of digit-serial signal processing architectures , 1991 .
[3] Joseph Cavanagh,et al. Digital Computer Arithmetic , 1983 .
[4] Homayoon Sam,et al. A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations , 1990, IEEE Trans. Computers.
[5] R. Gnanasekaran,et al. A Fast Serial-Parallel Binary Multiplier , 1985, IEEE Transactions on Computers.
[6] Tomás Lang,et al. Fast Multiplication Without Carry-Propagate Addition , 1990, IEEE Trans. Computers.
[7] Barrie Hayes-Gill,et al. Novel pipelined serial/parallel multiplier , 1990 .
[8] John G. McWhirter,et al. Some Systolic Array Developments in the United Kingdom , 1987, Computer.
[9] Peter F. Corbett,et al. Digit-serial processing techniques , 1990 .
[10] M. Ibrahim Sezan,et al. Digital video standards conversion in the presence of accelerated motion , 1994 .
[11] T.-Y. Chang,et al. Design and analysis of VLSI-based parallel multipliers , 1990 .
[12] John V. McCanny,et al. OPTIMISED BIT LEVEL SYSTOLIC ARRAY FOR CONVOLUTION. , 1984 .
[13] Milos D. Ercegovac,et al. On-Line Arithmetic: An Overview , 1984, Optics & Photonics.
[14] Magdy Bayoumi,et al. Testing of a NORA CMOS serial-parallel multiplier , 1989 .
[15] Shaler G. Smith,et al. Radix-4 modules for high-performance bit-serial computation , 1987 .
[16] John G. McWhirter,et al. Completely iterative, pipelined multiplier array suitable for VLSI , 1982 .
[17] Mary Jane Irwin,et al. Digit-Pipelined Arnthmetic as Illustrated by the Paste-Up System: A Tutorial , 1987, Computer.
[18] J. L. Meador,et al. A nonredundant-radix-4 serial multiplier , 1989 .
[19] Andrew D. Booth,et al. A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .
[20] Renato De Mori,et al. A recursive algorithm for binary multiplication and its implementation , 1985, TOCS.
[21] Mark Horowitz,et al. SPIM: a pipelined 64*64-bit iterative multiplier , 1989 .