Design of a 1.1 GSps 12 bit digital to analog convertor with 56 dBc SFDR at Nyquist frequency

High speed digital to analog convertor (DAC) is a key component in software defined radio systems, digital radars and wide band arbitrary waveform generators. In those applications, the performance of the DAC, especially the wideband dynamic range, is important in determining the system performance. In this paper we present a high speed 12 bit current steering DAC with optimized wideband performance. Theoretical analysis and optimizing strategy are present in this paper along with circuit details and measurement results. Experimental results reveal the proposed circuit is capable to operate up to 1.1 GSps. The measured spurious free dynamic range (SFDR) at low frequency is above 70 dBc at 1.1 GHz of sample rate. The SFDR is better than 56 dBc from DC to Nyquist frequency.

[1]  K. Bult,et al.  A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2 , 1998, IEEE J. Solid State Circuits.

[2]  Brian Miller,et al.  A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz ${\rm f}_{\rm T}$ BiCMOS Process , 2012, IEEE Journal of Solid-State Circuits.

[3]  Sung-Mo Kang,et al.  1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[4]  Kwang-Hyun Baek,et al.  A 1.6GS/s 12b return-to-zero GaAs RF DAC for multiple Nyquist operation , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[5]  Yu Lin,et al.  A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$60 dBc Beyond 1 GHz in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[6]  Ko-Chi Kuo,et al.  A Switching Sequence for Linear Gradient Error Compensation in the DAC Design , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.