A size sensitivity method for interactive CMOS circuit sizing

A new device sizing method for CMOS analog integrated circuit is proposed. This method employs graphical sensitivity curves of certain performance metric with respect to device sizes, called size sensitivity, to guide the designer to choose proper device sizes semi-automatically. It is shown that the plot of sensitivity curves in the frequency-domain can exhibit quantitative performance dependence to device sizes nearby dominant pole/zero locations. For accurate sensitivity calculation, the dependence on dc sensitivity in the computation of ac sensitivity to device size is emphasized and an EKV model-based implementation is outlined. The proposed graphical semi-automatic analog sizing methodology differentiates itself from the traditional black-box approaches with which the user has no interference in the optimization process. An interactive semi-automatic analog sizing tool with a graphical interface allows the user to decide which device sizes are more rewarding to tune. An operational amplifier is sized by using the proposed interactive tool.

[1]  C.-J. Richard Shi,et al.  A Graph Reduction Approach to Symbolic Circuit Analysis , 2007, 2007 Asia and South Pacific Design Automation Conference.

[2]  Georges G. E. Gielen,et al.  Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Denis Flandre,et al.  A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA , 1996, IEEE J. Solid State Circuits.

[4]  D.M. Binkley,et al.  Tradeoffs and Optimization in Analog CMOS Design , 2008, 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems.

[5]  Pradip Mandal,et al.  CMOS op-amp sizing using a geometric programming formulation , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Dennis L. Young,et al.  Application of statistical design and response surface methods to computer-aided VLSI device design , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Guoyong Shi,et al.  Variational analog integrated circuit design via symbolic sensitivity analysis , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[8]  Lawrence Pillage,et al.  Electronic Circuit & System Simulation Methods (SRE) , 1998 .

[9]  E. Vittoz,et al.  Charge-Based MOS Transistor Modeling , 2006 .

[10]  Helmut E. Graeb.  ITRS 2011 Analog EDA Challenges and Approaches , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  Ranga Vemuri,et al.  Fast analog circuit synthesis using multiparameter sensitivity analysis based on element-coefficient diagrams , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

[12]  Robert Spence,et al.  The facilitation of insight for analog design , 1999 .

[13]  Ronald A. Rohrer,et al.  Electronic Circuit and System Simulation Methods , 1994 .

[14]  Hui Xu,et al.  Hierarchical symbolic sensitivity computation with applications to large amplifier circuit design , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[15]  Guoyong Shi,et al.  A design platform for analog device size sensitivity analysis and visualization , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

[16]  Vijay Devabhaktuni,et al.  A new approach to sizing analog CMOS building blocks using pre-compiled neural network models , 2012 .

[17]  Guoyong Shi.  Graph-Pair Decision Diagram Construction for Topological Symbolic Circuit Analysis , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Kurt Antreich,et al.  Automating the sizing of analog CMOS circuits by consideration of structural constraints , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[19]  Stephen P. Boyd,et al.  Optimal design of a CMOS op-amp via geometric programming , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Large-scale geometric programming for devices and circuits , 2008 .

[21]  Sheldon X.-D. Tan,et al.  Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Francisco V. Fernández,et al.  A Statistical Optimization-based Approach For Automated Sizing Of Analog Cells , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[23]  Ulf Schlichtmann,et al.  The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  Paul Jespers.  The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches , 2009 .

[25]  Jian Wang.  Response surface modeling for analog and mixed-signal design , 2008 .

[26]  Christian Enz,et al.  Charge-Based MOS Transistor Modeling: The EKV Model for Low-Power and RF IC Design , 2006 .

[27]  Willy Sansen,et al.  Analog Circuit Design Optimization based on Symbolic Simulation and Simulated Annealing , 1989, ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference.

[28]  J. M. Rochelle,et al.  A CAD methodology for optimizing transistor current and sizing in analog CMOS design , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Donald Sarason.  Complex Function Theory , 2007 .

[30]  E. Vittoz,et al.  An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications , 1995 .

[31]  Guoyong Shi,et al.  Symbolic behavioral modeling for slew and settling analysis of operational amplifiers , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[32]  Georges G. E. Gielen,et al.  Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[33]  Huiying Yang,et al.  Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[34]  Guoyong Shi,et al.  A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits , 2011, Analog Integrated Circuits and Signal Processing.

[35]  Huiying Yang,et al.  SYMBOLIC SENSITIVITY ANALYSIS TECHNIQUES AND APPLICATIONS IN ANALOG CIRCUIT SYNTHESIS , 2007 .

[36]  Helmut Graeb,et al.  Analog Design Centering and Sizing , 2007 .

[37]  Ronald A. Rohrer,et al.  Pole and zero sensitivity calculation in asymptotic waveform evaluation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..