Decoding of Rate k/n Convolutional Codes in VLSI

A systematic procedure for an efficient VLSI implementation of the Viterbi algorithm for decoding convolutional codes is presented. This implementation is based on a network of simple processors, each performing an add-compare-select and branch-generation operation, that reside on a single die and are connected to execute the Viterbi algorithm in a highly parallel way. The chip area of such implementations will depend on the processor interconnections, which in turn depend on the state transition diagram of the convolutional encoder (or dual encoder). It is shown that for all rate 1/n convolutional codes generated by feed-forward FIR encoders the encoder state transition diagram, which is described by a de Bruijn graph, can be mapped by a simple equivalence relation to a well-known interconnection scheme in parallel processing referred to as the shuffle-exchange network, for which layout techniques that achieve a proven lower bound on implementation area in a VLSI medium have been established. These results are then extended to rate 1/n codes generated by (IIR) encoders containing feedback. Finally, in the case of general (feed-forward and feedback) rate k/n convolutional encoders it is shown that the state transition diagram of either the encoder or the dual encoder can be always mapped to the Cartesian product of de Bruijn graphs, and therefore of shuffle-exchange graphs; the point is that optimum VLSI layouts for the Cartesian product are easier to obtain and much less complicated than any direct VLSI layouts for the original state transition diagram.