An Elitist Non-Dominated Multi-Objective Genetic Algorithm Based Temperature Aware Circuit Synthesis

PARAMETERS such as area, power, and delay of highly complex logic circuits used in the field of digital systems can be appropriately optimized by utilizing AND-XOR based circuits rather than AND-OR based Boolean function [1]-[2]. Besides, XOR-based circuits are well suited for testability [3]-[4] and easily mapped into the Field Programmable Gate Arrays (FPGAs). Minimization of ANDXOR nodes (area count) is possible by sharing the sub-functions/ product terms within the multi-output functions. With the reduction of node count, the signal transitions among the sub-function get reduced. ‘Espresso,’ the two-level AND-OR minimizer was developed to eliminate redundant literals from canonical form using unite function decomposition [5]. Low power approaches are established by searching a suitable input variable polarity for maximum sharing of internal nodes to reduce the switching activity of a Boolean function [6]-[8]. There are several sub-classes of AND-XOR circuit synthesis which are of interest. The most general 2-level AND-XOR form is EXOR Sum-Of-Product (ESOP). Due to its non-canonical nature, ESOPs are very hard for optimization. It is observed that any Boolean function can be represented in modulo-2 AND-XOR based algebraic expressions. These expressions are elaborated with the help of Davio functions [9], and are termed as Reed-Muller (RM) expansions. A Boolean function represented in RM form is unique and canonical in nature, consumes less area, reduces power dissipation, and is in readily testable form [4]-[6], [8]. Depending on application-specific advantages, RM circuits are represented in the Positive Polarity Reed-Muller (PPRM) expansion, Fixed Polarity Reed-Muller (FPRM) expansion and Mixed Polarity Reed-Muller (MPRM) expansion. A thorough search on literature review has shown that optimization of MPRM is superior over the FPRM expansions on circuit performance regarding the area, switching activity (dynamic power) and/or delay [6]-[8], [10]-[11]. A fast minimization algorithm (FMA) using the binary differential evolution (BDE) method to minimize the FPRM product term is proposed in [12]. A comparative study of proposed FMA with the genetic algorithm (GA) and simulated annealing genetic algorithm (SAGA) is also reported. An incompletely specified FPRM (ISFPRM) acquisition algorithm is proposed by He et al. in [13]. The authors proposed a chromosome conversion technique to convert zero polarity ISFPRM to the FPRM for power reduction. A hybrid simulated annealing (SA) and discrete particle swarm optimization (DPSO) based area optimization approach is proposed in [14]. Authors in [8], considered the NSGA-II algorithm to find an optimal polarity for power and area optimization of MPRM network. Authors in [8] proposed a chromosome encoding method based on ternary input polarity and binary don’t care allocation. By exploiting the don’t care condition, authors in [15] proposed a delay optimization approach for MPRM based logic. In [15], the authors minimized the weighted Keywords

[1]  Hafizur Rahaman,et al.  Testable design of AND-EXOR logic networks with universal test sets , 2009, Comput. Electr. Eng..

[2]  Tsutomu Sasao,et al.  Switching Theory for Logic Synthesis , 1999, Springer US.

[3]  Neil Urquhart,et al.  Manipulation and optimisation techniques for Boolean logic , 2010, IET Comput. Digit. Tech..

[4]  Jianping Hu,et al.  Novel Synthesis and Optimization of Multi-Level Mixed Polarity Reed-Muller Functions , 2005, Journal of Computer Science and Technology.

[5]  Lin Wang.  Fast Algorithms for thermal-Aware floorplanning , 2014, J. Circuits Syst. Comput..

[6]  Apangshu Das and Sambhu Nath Pradhan.  Thermal-aware Output Polarity Selection Based on And-Inverter Graph Manipulation , 2019 .

[7]  Sambhu Nath Pradhan,et al.  Area, power and temperature optimization during binary decision diagram based circuit synthesis , 2017, 2017 Devices for Integrated Circuit (DevIC).

[8]  Limin Xiao,et al.  POA-FPRMs: Power Optimization Approach of Fixed Polarity Reed-Muller Expressions for Incompletely Specified Boolean Functions , 2019 .

[9]  Santanu Chattopadhyay,et al.  AND-XOR Network Synthesis with Area-Power Trade-off , 2008 .

[10]  Sambhu Nath Pradhan,et al.  Area-Power-Temperature Aware AND-XOR Network Synthesis Based on Shared Mixed Polarity Reed-Muller Expansion , 2018 .

[11]  Limin Xiao,et al.  Fast Minimization of Fixed Polarity Reed-Muller Expressions , 2019, IEEE Access.

[12]  Kevin Skadron,et al.  HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  A. Das,et al.  An elitist area-power density trade-off in VLSI floorplan using genetic algorithm , 2012, 2012 7th International Conference on Electrical and Computer Engineering.

[14]  Shahin Nazarian,et al.  Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods , 2006, Proceedings of the IEEE.

[15]  Kevin Skadron,et al.  A Case for Thermal-Aware Floorplanning at the Microarchitectural Level , 2005, J. Instr. Level Parallelism.

[16]  Li Shang,et al.  Thermal crisis: challenges and potential solutions , 2006, IEEE Potentials.

[17]  J. M. Saul.  Logic synthesis for arithmetic circuits using the Reed-Muller representation , 1992, [1992] Proceedings The European Conference on Design Automation.

[18]  Sambhu Nath Pradhan,et al.  Thermal aware FPRM based AND-XOR network synthesis of logic circuits , 2015, 2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS).

[19]  Vivek Rai,et al.  Thermal-Aware Partitioning and Encoding of Power-Gated FSM , 2019, J. Circuits Syst. Comput..

[20]  Limin Xiao,et al.  EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model , 2017, Frontiers of Computer Science.

[21]  Michelle Zhu,et al.  Verification method for area optimization of mixed-polarity Reed-Muller logic circuits , 2018 .

[22]  Stephen H. Gunther,et al.  Managing the Impact of Increasing Microprocessor Power Consumption , 2001 .

[23]  Santanu Chattopadhyay,et al.  Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach , 1996, IEEE Trans. Computers.

[24]  S AURABH C HAUDHURY.  Output phase assignment for area and power minimization in PLAs , 2006 .

[25]  Limin Xiao,et al.  A Power and Area Optimization Approach of Mixed Polarity Reed-Muller Expression for Incompletely Specified Boolean Functions , 2017, Journal of Computer Science and Technology.

[26]  C. L. Liu,et al.  Low power logic synthesis for XOR based circuits , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[27]  Tsutomu Sasao,et al.  Logic Synthesis and Optimization , 1997 .

[28]  Sambhu Nath Pradhan,et al.  Thermal aware output polarity selection of programmable logic arrays , 2015, 2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV).

[29]  Sambhu Nath Pradhan,et al.  Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits , 2016, VLSI Design.

[30]  Li Hui,et al.  Low power mapping for AND/XOR circuits and its application in searching the best mixed-polarity , 2011 .

[31]  Richard E. Ladner,et al.  On the Structure of Polynomial Time Reducibility , 1975, JACM.

[32]  Eric Mayer,et al.  Synthesis Of Finite State Machines Logic Optimization , 2016 .

[33]  Kalyanmoy Deb,et al.  A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..

[34]  Santanu Chattopadhyay,et al.  Fixed Polarity Reed-Muller Network Synthesis and Its Application in AND-OR/XOR-based Circuit Realization with Area-Power Trade-off , 2008 .