A 1.5μW 1V 2nd-Order ΔΣ Sensor Front-End with Signal Boosting and Offset Compensation for a Capacitive 3-Axis Micro-Accelerometer
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Kari Halonen | Erkka Laulainen | Mikko Saukoski | Marko Kosunen | Mika Kämäräinen | Matti Paavola | Lauri Koskinen
[1] Yukihiro Fujimoto,et al. A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture , 1993 .
[2] Paul R. Gray,et al. A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.
[3] Kari Halonen,et al. A 62μA Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[4] Ramesh Harjani,et al. An integrated low-voltage class AB CMOS OTA , 1999 .
[5] Gabor C. Temes,et al. High-accuracy circuits for on-chip capacitance ratio testing or sensor readout , 1994 .
[6] H. Kawaguchi,et al. Managing subthreshold leakage in charge-based analog circuits with low-V/sub TH/ transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS) , 2006, IEEE Journal of Solid-State Circuits.
[7] M. Steyaert,et al. A 0.8-V, 8-/spl mu/W, CMOS OTA with 50-dB gain and 1.2-MHz GBW in 18-pF load , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).