Automatic clock tree generation in ASIC designs

This paper presents a methodology for automatic generation of clock trees in an ASIC design at the schematic/netlist level. New algorithms and heuristics are described: they have been inserted with success in an industrial ASIC design flow, after the logic synthesis and optimization step. Our algorithms, by different heuristics, take particularly into account those elements connected as transmitter-receiver couples which represent the most critical configurations for circuit synchronization. Improvement of clock tree performance has also been obtained by means of an interaction strategy between logic and physical design phases.<<ETX>>