Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips

[1]  Qiang Fu,et al.  Characterizing Intra-Die Spatial Correlation Using Spectral Density Method , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[2]  Sherief Reda,et al.  Within-die process variations: How accurately can they be statistically modeled? , 2008, 2008 Asia and South Pacific Design Automation Conference.

[3]  Farid N. Najm,et al.  Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[4]  P. Diggle,et al.  Model‐based geostatistics , 2007 .

[5]  Jinjun Xiong,et al.  Robust Extraction of Spatial Correlation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Yu Cao,et al.  Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[7]  Yu Hen Hu,et al.  Statistical timing analysis with path reconvergence and spatial correlations , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[8]  Sachin S. Sapatnekar,et al.  Statistical timing analysis under spatial correlations , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Costas J. Spanos,et al.  Modeling within-die spatial correlation effects for process-design co-optimization , 2005, Sixth international symposium on quality electronic design (isqed'05).

[10]  Vijay Pitchumani Embedded tutorial I: design for manufacturability , 2005, ASP-DAC '05.

[11]  Sani R. Nassif Design for Variability in DSM Technologies , 2000 .

[12]  Noel A Cressie,et al.  Statistics for Spatial Data. , 1992 .