Test and Repair Methodology for FinFET-Based Memories

FinFET transistors are commonly acknowledged as the most promising technology able to play a crucial role to route the development of rapidly growing modern silicon industry. Embedded memories, based on FinFET transistors, lead to new defect types that can require new embedded test and repair solutions. To investigate FinFET-specific faults, the existing fault models and detection techniques are not enough because of the spatial structure of FinFET transistors. This paper presents the results of the comprehensive study carried out for FinFET-based memories based on a new fault modeling and test algorithm creation strategy. The proposed solution is validated on several real FinFET-based embedded memory technologies.

[1]  W. Marsden I and J , 2012 .

[2]  G. Gaydadjiev,et al.  A Fault Primitive Based Analysis of Dynamic Memory Faults , 2003 .

[3]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[4]  Tsu-Jae King,et al.  FinFETs for nanoscale CMOS digital integrated circuits , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[5]  Hui-Wen Cheng,et al.  16-nm multigate and multifin MOSFET device and SRAM circuits , 2010, 2010 International Symposium on Next Generation Electronics.

[6]  Said Hamdioui,et al.  Linked faults in random access memories: concept, fault models, test algorithms, and industrial results , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Chen-Wei Lin,et al.  Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[8]  Qiang Xu,et al.  On modeling faults in FinFET logic circuits , 2012, 2012 IEEE International Test Conference.

[9]  Víctor H. Champac,et al.  Testing of Stuck-Open Faults in Nanometer Technologies , 2012, IEEE Design & Test of Computers.

[10]  A. N. Bhoj,et al.  Fault Models for Logic Circuits in the Multigate Era , 2012, IEEE Transactions on Nanotechnology.

[11]  Yervant Zorian,et al.  An effective solution for building memory BIST infrastructure based on fault periodicity , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[12]  K. Roy,et al.  Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era , 2007, IEEE Transactions on Electron Devices.

[13]  Yervant Zorian,et al.  Impact of process variations on read failures in SRAMs , 2013, East-West Design & Test Symposium (EWDTS 2013).

[14]  Yervant Zorian,et al.  A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Arnaud Virazel,et al.  Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories , 2005, J. Electron. Test..

[16]  Niraj K. Jha,et al.  Fault modeling for FinFET circuits , 2010, 2010 IEEE/ACM International Symposium on Nanoscale Architectures.

[17]  Arnaud Virazel,et al.  Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[18]  N. Collaert,et al.  Review of FINFET technology , 2009, 2009 IEEE International SOI Conference.

[19]  Min-hwa Chi Challenges in Manufacturing FinFET at 20 nm node and beyond , 2012 .

[20]  Víctor H. Champac,et al.  Stuck-Open Fault Leakage and Testing in Nanometer Technologies , 2009, 2009 27th IEEE VLSI Test Symposium.

[21]  Yervant Zorian,et al.  Minimal march test algorithm for detection of linked static faults in random access memories , 2006, 24th IEEE VLSI Test Symposium.

[22]  P. D. Ye,et al.  First experimental demonstration of gate-all-around III–V MOSFETs by top-down approach , 2011, 2011 International Electron Devices Meeting.

[23]  Zheng Guo,et al.  SRAM Read/Write Margin Enhancements Using FinFETs , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Alfredo Benso,et al.  Automatic March tests generation for static and dynamic faults in SRAMs , 2005, European Test Symposium (ETS'05).