Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time

In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause is electric field enhancement caused by metal precipitates located at the gate-drain overlap region.

[1]  T. Fukai,et al.  Effects of the Scaling on n+/p Junction Leakage Characteristics , 1999 .

[2]  H. Iwai,et al.  Local-field-enhancement model of DRAM retention failure , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[3]  M. Moniwa,et al.  Statistical pn junction leakage model with trap level fluctuation for Tref (refresh time)-oriented DRAM design , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[4]  K. Ohyu,et al.  A mechanism and a reduction technique for large reverse leakage current in p-n junctions , 1995 .

[5]  M. Inuishi,et al.  Impact of the two traps related leakage mechanism on the tail distribution of DRAM retention characteristics , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[6]  T. Hamamoto,et al.  On the retention time distribution of dynamic random access memory (DRAM) , 1998 .