A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO

An all-digital phase-locked loop (ADPLL) with all components working with time interval or period signals is demonstrated. The ADPLL consists mainly of a free-running ring oscillator (FRO), a time to digital converter (TDC), a digitally controlled oscillator (DCO), a digital divider and a digital loop filter. In the proposed architecture, the TDC and DCO have an equal time resolution from the common FRO. The digital divider keeps the loop gain constant when the frequency multiplication factor changes. As a result, the ADPLL is inherently stable regardless of the variations of the process, supply voltage and temperature (PVT). The ADPLL is fabricated in 0.13 ¿m CMOS process. Measurement results show that it works well over wide operation conditions, with the input frequencies ranging from 37.5 KHz to 25 MHz, frequency multiplication factors from 10 to 255, output frequencies from 10 MHz to 500 MHz, and supply voltages from 0.6 V to 1.6 V.

[1]  Takamoto Watanabe,et al.  An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time , 2003 .

[2]  Poras T. Balsara,et al.  Phase-domain all-digital phase-locked loop , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Jaeha Kim,et al.  Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL , 2003 .

[4]  Poras T. Balsara,et al.  1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  J.A. Tierno,et al.  A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI , 2008, IEEE Journal of Solid-State Circuits.

[6]  K. Muhammad,et al.  All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.

[7]  Liming Xiu,et al.  A "flying-adder" architecture of frequency and phase synthesis with scalability , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[8]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[9]  J. Lundberg,et al.  An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors(Special Issue on the 1994 VLSI Circuits Symposium) , 1995 .

[10]  J. Meiners,et al.  A novel all-digital PLL with software adaptive filter , 2004, IEEE Journal of Solid-State Circuits.

[11]  Jin-Sheng Wang,et al.  A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).