An integrated 17 GHz front-end for ISM/WLAN applications in 0.13 /spl mu/m CMOS

This paper presents an integrated front-end for ISM/WLAN applications at 17.3 GHz in 0.13 /spl mu/m standard CMOS. The front-end chip includes an inductive source-degenerated low noise amplifier (LNA), a transformer-based Gilbert-mixer, an intermediate frequency (IF) amplifier and a buffer for the local oscillator (LO) input. The integrated receiver front-end achieves a gain of 34.7 dB, a SSB noise figure of 6.6 dB, an input. IP3 of -34.4 dBm and an input 1dB compression point of -39 dBm and consumes only 70 mW at a power supply voltage of 1.5 V.

[1]  Arpad L. Scholtz,et al.  Modeling of monolithic lumped planar transformers up to 20 GHz , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[2]  G. Knoblinger,et al.  A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

[3]  Asad A. Abidi,et al.  A 900 MHz dual conversion low-IF GSM receiver in 0.35 μm CMOS , 2001 .

[4]  A. Abidi,et al.  A 900 MHz dual conversion low-IF GSM receiver in 0.35 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[5]  Xiang Guan,et al.  A 24-GHz CMOS front-end , 2004, IEEE Journal of Solid-State Circuits.

[6]  A. Hajimiri,et al.  A 24GHz CMOS front-end , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[7]  B. Jagannathan,et al.  A 17.1 to 17.3 GHz image-reject down-converter with phase-tunable LO using 3/spl times/ subharmonic injection locking , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).