Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs

In this paper, we propose the employment of fast targeted programs (diagnostic micro-viruses) that aim to stress individually the main hardware components of a multicore CPU architecture which most likely determine the limits of voltage scaling, i.e. safe Vmin values. We describe in detail the complex development process for the diagnostic micro-viruses and their comprehensive validation in modern multicore CPU hardware. The combined execution of the micro-viruses takes very short time compared to regular programs execution, and can quickly reveal the voltage limits of the cores and chips at voltage levels below nominal. The micro-virus based characterization flow requires orders of magnitude shorter time while it delivers virtually identical: (a) Vmin values for the different CPU chips, and (b) Vmin values for the different cores within a CPU chip. We evaluate our micro-viruses based characterization flow (and compare it to the SPEC-based flow) on three different chips (a nominal graded and two corner parts) of Applied Micro's X-Gene 2 micro-server family (with 8-core ARMv8-based CPUs manufactured in 28nm). We report detailed validation and evaluation results that prove the effectiveness of the micro-viruses for the fast and accurate identification of the voltage margins variability among the chips and the cores of a multicore CPU.

[1]  Meeta Sharma Gupta,et al.  An event-guided approach to reducing voltage noise in processors , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Dimitris Gizopoulos,et al.  Voltage margins identification on commercial x86-64 multicore microprocessors , 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

[3]  Tsuyoshi Murata,et al.  {m , 1934, ACML.

[4]  Alaa R. Alameldeen,et al.  Trading off Cache Capacity for Reliability to Enable Low Voltage Operation , 2008, 2008 International Symposium on Computer Architecture.

[5]  Lizy Kurian John,et al.  Automated di/dt stressmark generation for microprocessor power delivery networks , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[6]  Wei Wu,et al.  Improving cache lifetime reliability at ultra-low voltages , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[7]  Margaret Martonosi,et al.  Control techniques to eliminate voltage emergencies in high performance processors , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[8]  Sudeep Pasricha,et al.  VARSHA: Variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[9]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[10]  Diana Marculescu,et al.  Variation-aware dynamic voltage/frequency scaling , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[11]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[12]  William J. Bowhill,et al.  A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers , 2011, 2011 IEEE International Solid-State Circuits Conference.

[13]  P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

[14]  Jingwen Leng,et al.  Adaptive guardband scheduling to improve system-level efficiency of the POWER7+ , 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[15]  Bishop Brock,et al.  Active management of timing guardband to save energy in POWER7 , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[16]  Shidhartha Das,et al.  Analysis of adaptive clocking technique for resonant supply voltage noise mitigation , 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[17]  Michael D. Smith,et al.  Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[18]  Josep Torrellas,et al.  Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors , 2008, 2008 International Symposium on Computer Architecture.

[19]  Rakesh Kumar,et al.  Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation , 2016, ISCA.

[20]  Richard E. Kessler,et al.  Page placement algorithms for large real-indexed caches , 1992, TOCS.

[21]  Lizy Kurian John,et al.  AUDIT: Stress Testing the Automatic Way , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[22]  Radu Teodorescu,et al.  Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors , 2013, ISCA.

[23]  Lizy Kurian John,et al.  MAximum Multicore POwer (MAMPO) — An automatic multithreaded synthetic power virus generation framework for multicore systems , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

[24]  Radu Teodorescu,et al.  Authenticache: Harnessing cache ECC for system authentication , 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[25]  Shidhartha Das,et al.  Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs , 2017, 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[26]  Meeta Sharma Gupta,et al.  Voltage emergency prediction: Using signatures to reduce operating margins , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[27]  Pradip Bose,et al.  Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[28]  Radu Teodorescu,et al.  Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[29]  Meeta Sharma Gupta,et al.  Towards a software approach to mitigate voltage emergencies , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[30]  Matteo Sonza Reorda,et al.  Microprocessor Software-Based Self-Testing , 2010, IEEE Design & Test of Computers.

[31]  Siddharth Garg,et al.  Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[32]  Xiang Pan,et al.  VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[33]  Eli Chiprout,et al.  A microarchitecture-based framework for pre- and post-silicon power delivery analysis , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[34]  Josep Torrellas,et al.  ScalCore: Designing a core for voltage scalability , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[35]  T. N. Vijaykumar,et al.  Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

[36]  Meeta Sharma Gupta,et al.  Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[37]  Shidhartha Das,et al.  14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[38]  Dimitris Gizopoulos,et al.  Software-Based Self-Test for Small Caches in Microprocessors , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[39]  Meeta Sharma Gupta,et al.  DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[40]  Gernot Heiser,et al.  Dynamic voltage and frequency scaling: the laws of diminishing returns , 2010 .