Temperature Dependent Test Scheduling for Multi-core System-on-Chip

Recent research has shown that some defects are detect resilient under normal or high temperature, therefore tests for those defects must be applied under lower temperature. On the other hand, some tests need to be applied under high temperature to improve the detection sensitivity. Thus temperature dependent testing which applies tests at different temperature ranges is needed. This paper discusses and gives a formulation of the temperature dependent test scheduling problem. In the proposed test scheduling scheme, each test is associated with a lower temperature bound and an upper temperature bound to define the temperature range within which the test must be applied. A list schedule based test scheduling algorithm is proposed to find the earliest starting time of each test. Cooling period is inserted when the core temperature is too high and heating sequence is applied when the core temperature is below the required specified temperature for the core. Simulation studies are performed for ITC'02 SoC benchmarks and test scheduling results are shown.

[1]  Krishnendu Chakrabarty,et al.  Test Resource Partitioning for System-on-a-Chip , 2002, Frontiers in electronic testing.

[2]  Edward J. McCluskey,et al.  Cold delay defect screening , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[3]  Parameswaran Ramanathan,et al.  Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Petru Eles,et al.  Multi-temperature testing for core-based system-on-chip , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[5]  Prabhat Kumar,et al.  Temperature-aware test scheduling for multiprocessor systems-on-chip , 2008, ICCAD 2008.

[6]  Li Shang,et al.  Temperature-aware test scheduling for multiprocessor systems-on-chip , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[7]  Kaushik Roy,et al.  Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Krishnendu Chakrabarty,et al.  Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Kaushik Roy,et al.  Multiple-parameter CMOS IC testing with increased sensitivity for I/sub DDQ/ , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[10]  Parameswaran Ramanathan,et al.  Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies , 2009, 2009 Asian Test Symposium.

[11]  Bernd Becker,et al.  On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  H. Fujiwara,et al.  Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip , 2007, 16th Asian Test Symposium (ATS 2007).

[13]  Petru Eles,et al.  Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving , 2008, J. Electron. Test..

[14]  W. Robert Daasch,et al.  Minimum testing requirements to screen temperature dependent defects , 2004, 2004 International Conferce on Test.

[15]  Bernd Becker,et al.  On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing , 2008, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Parameswaran Ramanathan,et al.  Thermal-Aware Test Scheduling Using On-chip Temperature Sensors , 2011, 2011 24th Internatioal Conference on VLSI Design.

[17]  V. Kamakoti,et al.  Impact of Temperature on Test Quality , 2010, 2010 23rd International Conference on VLSI Design.

[18]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[20]  Parameswaran Ramanathan,et al.  Test Scheduling for Circuits in Micron to Deep Submicron Technologies , 2010 .

[21]  Jaume Segura,et al.  CMOS Electronics: How It Works, How It Fails , 2004 .

[22]  Chunsheng Liu,et al.  Thermal-aware test scheduling and hot spot temperature minimization for core-based systems , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[23]  Wayne M. Needham,et al.  High volume microprocessor test escapes, an analysis of defects our tests are missing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[24]  Erik Jan Marinissen,et al.  A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.

[25]  Kevin Skadron,et al.  A Case for Thermal-Aware Floorplanning at the Microarchitectural Level , 2005, J. Instr. Level Parallelism.

[26]  Irith Pomeranz,et al.  Improving the Detectability of Resistive Open Faults in Scan Cells , 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[27]  W. Robert Daasch,et al.  Detection of temperature sensitive defects using ZTC , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[28]  Edward J. McCluskey,et al.  Testing for resistive opens and stuck opens , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[29]  Kevin Skadron,et al.  HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.