Novel linear analog-adder using a-IGZO TFTs

A novel linear analog adder is proposed only with n-type enhancement IGZO TFTs that computes summation of four voltage signals. However, this design can be easily extended to perform summation of higher number of signals, just by adding a single TFT for each additional signal in the input block. The circuit needs few number of transistors, only a single power supply irrespective of the number of voltage signals to be added, and offers good accuracy over a reasonable range of input values. The circuit was fabricated on glass substrate with the annealing temperature not exceeding 200° C. The circuit performance is characterized from measurements under normal ambient at room temperature, with a power supply voltage of 12 V and a load of ≈ 4 pF. The designed circuit has shown a linearity error of 2.3% (until input signal peak to peak value is 2 V), a power consumption of 78 μW and a bandwidth of ≈ 115 kHz, under the worst case condition (when it is adding four signals with the same frequency). In this test setup, it has been noticed that the second harmonic is 32 dB below the fundamental frequency component. This circuit could offer an economic alternative to the conventional approaches, being an important contribution to increase the functionality of large area flexible electronics.

[1]  C. Zysset,et al.  IGZO TFT-Based All-Enhancement Operational Amplifier Bent to a Radius of 5 mm , 2013, IEEE Electron Device Letters.

[2]  Ahmed Gharbiya,et al.  On the implementation of input-feedforward delta-sigma modulators , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  H. Ohta,et al.  Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors , 2004, Nature.

[4]  C. RoyChaudhuri,et al.  Analog ASIC for improved temperature drift compensation of a high sensitive porous silicon pressure sensor , 2011 .

[5]  Byung-Do Yang,et al.  A Transparent Logic Circuit for RFID Tag in a‐IGZO TFT Technology , 2013 .

[6]  Robert W. Newcomb,et al.  A neural-type pool arithmetic unit , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[7]  M.C.H. Cheng,et al.  Linear composite MOSFET: theory, design, and applications , 1993 .

[8]  H. Ozaki,et al.  20-µW operation of an a-IGZO TFT-based RFID chip using purely NMOS “active” load logic gates with ultra-low-consumption power , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[9]  Arthur H. M. van Roermund,et al.  A 6b 10MS/s current-steering DAC manufactured with amorphous Gallium-Indium-Zinc-Oxide TFTs achieving SFDR > 30dB up to 300kHz , 2012, 2012 IEEE International Solid-State Circuits Conference.

[10]  H.S. Abdel-Aty-Zohdy,et al.  Analog computational circuits for neural network implementations , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[11]  Hicham Chaoui.  CMOS analogue adder , 1995 .

[12]  J. Ramirez-Angulo,et al.  A compact high frequency VLSI differential analog adder , 1996, Proceedings of the 39th Midwest Symposium on Circuits and Systems.

[13]  Jang-Yeon Kwon,et al.  42.2: World's Largest (15‐inch) XGA AMLCD Panel Using IGZO Oxide TFT , 2008 .

[14]  Pedro Barquinha,et al.  Analog Circuits With High-Gain Topologies Using a-GIZO TFTs on Glass , 2015, Journal of Display Technology.