论文信息 - A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS

A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS

Fractional-N PLLs [1-3] are widely used due to their fine frequency resolution. However, their phase noise performance is typically worse than the integer-N [4, 5, 6] counterpart due to the quantization noise of the delta-sigma modulator (DSM). In this paper, we propose a low-noise fractional-N PLL that achieves best-case figure-of-merit (FOM) of -240.3dB, rms jitter of 255fsrms and worst-case fractional spur of -53.9dBc by using an 800MHz reference generated from a low-noise reference-injected integer-N PLL.

SeongHwan Cho | Dongmin Park

[1] Matthew Z. Straayer,et al. A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, IEEE Journal of Solid-State Circuits.

[2] Giovanni Marzin,et al. A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power , 2011, 2011 IEEE International Solid-State Circuits Conference.

[3] B. Helal,et al. A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop , 2008, IEEE Journal of Solid-State Circuits.

[4] Sander Gierkink. An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5] T. Cho,et al. A low spur fractional-N digital PLL for 802.11 a/b/g/n/ac with 0.19 psrms jitter , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.