A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation
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Igor Arsovski | Travis Hebig | Daniel Dobson | Reid Wistort | I. Arsovski | Travis Hebig | Daniel Dobson | R. Wistort
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