Research and Design of Reconfigurable Security Resource Pool Framework

In the era of cloud computing and big data, the demand for centralized security services is highlighted. In this paper we survey the existing security solutions which are proposed to provide the information security level protection services in the cloud, and present a reconfigurable security resource pool framework to provide security services to the tenants on demand. In the framework, Field Programmable Gate Arrays that support dynamic and partial reconfiguration capabilities are used as the computing entity. Finally, a prototype system is designed on the OpenStack platform. The analysis shows that the framework can not only ensure the security and reliability of the system, but also improve the utilization of FPGA resources.

[1]  Douglas L. Maskell,et al.  Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? , 2016, 2016 IEEE 14th Intl Conf on Dependable, Autonomic and Secure Computing, 14th Intl Conf on Pervasive Intelligence and Computing, 2nd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech).

[2]  Kizheppatt Vipin,et al.  Virtualized FPGA Accelerators for Efficient Cloud Computing , 2015, 2015 IEEE 7th International Conference on Cloud Computing Technology and Science (CloudCom).

[3]  Eriko Nurvitadhi,et al.  Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? , 2017, FPGA.

[4]  Yu Zhang,et al.  Enabling FPGAs in the cloud , 2014, Conf. Computing Frontiers.

[5]  Andrew Putnam.  Large-scale reconfigurable computing in a microsoft datacenter , 2014, 2014 IEEE Hot Chips 26 Symposium (HCS).

[6]  Paolo Ienne,et al.  Virtualized Execution Runtime for FPGA Accelerators in the Cloud , 2017, IEEE Access.

[7]  Hari Angepat,et al.  A cloud-scale acceleration architecture , 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[8]  Dirk Koch,et al.  JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[9]  Cong Li,et al.  Kernel-based Virtual Machine , 2017 .

[10]  Shadi Aljawarneh,et al.  Cloud security engineering: Early stages of SDLC , 2017, Future Gener. Comput. Syst..

[11]  Kizheppatt Vipin,et al.  ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq , 2014, IEEE Embedded Systems Letters.

[12]  Cheng-Wen Wu,et al.  Single- and Multi-core Configurable AES Architectures for Flexible Security , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Jun Han,et al.  A low-complexity heterogeneous multi-core platform for security soc , 2010, 2010 IEEE Asian Solid-State Circuits Conference.

[14]  Qiang Liu,et al.  High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion , 2015, IET Comput. Digit. Tech..

[15]  Limin Xiao,et al.  High Performance Implementation of ARIA Encryption Algorithm on Graphics Processing Units , 2013, 2013 IEEE 10th International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing.

[16]  Kizheppatt Vipin,et al.  DyRACT: A partial reconfiguration enabled accelerator and test platform , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

[17]  Kizheppatt Vipin,et al.  FPGA Dynamic and Partial Reconfiguration , 2018, ACM Comput. Surv..

[18]  Shadi Aljawarneh,et al.  Cloud Security Engineering: Avoiding Security Threats the Right Way , 2011, Int. J. Cloud Appl. Comput..