High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors

AbstractWe explore 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (∼108), low drain-induced barrier lowering (∼30 mV) and low subthreshold swing (∼80 mV/decade). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain (∼148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.

[1]  C. Lieber,et al.  Nanowire Nanosensors for Highly Sensitive and Selective Detection of Biological and Chemical Species , 2001, Science.

[2]  A. Rinzler,et al.  An Integrated Logic Circuit Assembled on a Single Carbon Nanotube , 2006, Science.

[3]  James R. Heath,et al.  Ultradense, deep subwavelength nanowire array photovoltaics as engineered optical thin films. , 2010, Nano letters.

[4]  Qian Wang,et al.  Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and Ring Oscillators , 2002, Nano Letters.

[5]  Charles M. Lieber,et al.  Coaxial silicon nanowires as solar cells and nanoelectronic power sources , 2007, Nature.

[6]  Bonnie A. Sheriff,et al.  A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre , 2007, Nature.

[7]  S.C. Rustagi,et al.  Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications , 2008, IEEE Transactions on Electron Devices.

[8]  Shashank Sharma,et al.  Surface Charge Density of Unpassivated and Passivated Metal-Catalyzed Silicon Nanowires , 2006 .

[9]  Donhee Ham,et al.  Nanotechnology: High-speed integrated nanowire circuits , 2005, Nature.

[10]  B. E. White,et al.  Impact of Deposition and Annealing Temperature on Material and Electrical Characteristics of ALD HfO2 , 2004 .

[11]  Donhee Ham,et al.  Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits , 2009, Proceedings of the National Academy of Sciences.

[12]  R. Rooyackers,et al.  A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node , 2004, IEEE Electron Device Letters.

[13]  Vincent M. Stanford,et al.  Metrology for the Electrical Characterization of Semiconductor Nanowires , 2008, IEEE Transactions on Electron Devices.

[14]  A. Hikavyy,et al.  Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography , 2007, 2007 IEEE Symposium on VLSI Technology.

[15]  D. Schroder.  Semiconductor Material and Device Characterization , 1990 .

[16]  Slobodan Mitrovic,et al.  Reduction of thermal conductivity in phononic nanomesh structures. , 2010, Nature nanotechnology.

[17]  Andrew R. Brown,et al.  Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .

[18]  J.D. Plummer,et al.  Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces , 1980, IEEE Transactions on Electron Devices.

[19]  Xiangfeng Duan,et al.  High-performance thin-film transistors using semiconductor nanowires and nanoribbons , 2003, Nature.

[20]  J. F. Conley,et al.  Atomic layer deposition of thin hafnium oxide films using a carbon free precursor , 2003 .

[21]  James R Heath,et al.  Complementary symmetry silicon nanowire logic: power-efficient inverters with gain. , 2006, Small.

[22]  J. Plummer,et al.  Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's , 1997, IEEE Electron Device Letters.

[23]  K. Onishi,et al.  Improvement of surface carrier mobility of HfO/sub 2/ MOSFETs by high-temperature forming gas annealing , 2003 .

[24]  S.C. Rustagi,et al.  CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach , 2007, IEEE Electron Device Letters.

[25]  Yuan Taur,et al.  Scaling of Nanowire Transistors , 2008, IEEE Transactions on Electron Devices.

[26]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .

[27]  Denis Flandre,et al.  Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode , 2005 .

[28]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[29]  James R Heath,et al.  Superlattice nanowire pattern transfer (SNAP). , 2008, Accounts of chemical research.

[30]  James R Heath,et al.  Two-dimensional single-crystal nanowire arrays. , 2007, Small.

[31]  N. Melosh,et al.  Ultrahigh-Density Nanowire Lattices and Circuits , 2003, Science.

[32]  Hsing-Hui Hsu,et al.  Fabrication and Characterization of Multiple-Gated Poly-Si Nanowire Thin-Film Transistors and Impacts of Multiple-Gate Structures on Device Fluctuations , 2008, IEEE Transactions on Electron Devices.

[33]  Y. Tosaka,et al.  Scaling theory for double-gate SOI MOSFET's , 1993 .

[34]  Michael C. McAlpine,et al.  Highly ordered nanowire arrays on plastic substrates for ultrasensitive flexible chemical sensors. , 2007, Nature materials.

[35]  William A. Goddard,et al.  Silicon nanowires as efficient thermoelectric materials , 2008, Nature.

[36]  Wei Lu,et al.  Synthesis and Fabrication of High‐Performance n‐Type Silicon Nanowire Transistors , 2004 .