Design and parallel testing of wafer scale linear arrays with high harvest rates
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[1] F. Baba,et al. 200-Mb wafer scale memory , 1990, 1990 Proceedings. International Conference on Wafer Scale Integration.
[2] Frank B. Manning,et al. An Approach to Highly Integrated, Computer-Maintained Cellular Arrays , 1977, IEEE Transactions on Computers.
[3] R. W. Horst. A linear-array WSI architecture for improved yield and performance , 1990, 1990 Proceedings. International Conference on Wafer Scale Integration.
[4] R.C. Aubusson,et al. Wafer-scale integration-a fault-tolerant procedure , 1978, IEEE Journal of Solid-State Circuits.
[5] Vishwani D. Agrawal. Comments on "An Approach to Highly Integrated Computer-Maintained Cellular Arrays" , 1979, IEEE Trans. Computers.