Design and parallel testing of wafer scale linear arrays with high harvest rates

Design for high harvest rates and parallel on-wafer diagnosis of linear arrays are described. A generalized loop-based approach to defect-tolerant wafer scale linear arrays is presented. In terms of harvest rate, the loop-based approach is significantly better than the traditional spiral approaches. Similar to the spiral approaches, the loop-based approach guarantees a fixed propagation delay between any logically consecutive cells after reconfiguration, independent of the fault distribution. However, the propagation delay is larger than that of the spiral approaches. Simulation-based harvest rates for four loop-based approaches are described. Application of boundary scan to parallel testing and on-wafer diagnosis of the arrays is also presented.<<ETX>>