Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET

The localized thermal effect caused by the self-heating effect (SE) becomes important for nanoscale 3-D transistors such as bulk FinFET because the thermal coupling from substrate is critical in such 3-D transistors. In this brief, we analyze the SE in 5-nm bulk FinFETs that are scaled down, following the International Technology Roadmap for Semiconductors. We systematically analyze the impact of key device parameters of bulk FinFET in view of the SE. Since the SE affects performance and reliability of transistors simultaneously, we define new figures of merit including ac delay and bias temperature instability for the first time, and it is found that the proper source/drain contact scheme design can achieve performance and reliability improvement at the same time in 5-nm bulk FinFET technology.

[1]  Jianping Guo,et al.  Localized thermal effect of sub-16nm FinFET technologies and its impact on circuit reliability designs and methodologies , 2015, 2015 IEEE International Reliability Physics Symposium.

[2]  M. Asheghi,et al.  Modeling and Data for Thermal Conductivity of Ultrathin Single-Crystal SOI Layers at High Temperature , 2006, IEEE Transactions on Electron Devices.

[3]  N. Xu,et al.  Investigation of Self-Heating Effect on Hot Carrier Degradation in Multiple-Fin SOI FinFETs , 2015, IEEE Electron Device Letters.

[4]  M. Shrivastava,et al.  Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures , 2012, IEEE Transactions on Electron Devices.

[5]  E. Pop,et al.  Thermal phenomena in nanoscale transistors , 2006, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems (IEEE Cat. No.04CH37543).

[6]  E. Pop,et al.  Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices] , 2003, IEEE International Electron Devices Meeting 2003.

[7]  Nobuyasu Beppu,et al.  Thermal-aware device design of nanoscale bulk/SOI FinFETs: Suppression of operation temperature and its variability , 2011, 2011 International Electron Devices Meeting.

[8]  K. Wu,et al.  Self-heating effect in FinFETs and its impact on devices reliability characterization , 2014, 2014 IEEE International Reliability Physics Symposium.

[9]  Chenming Hu,et al.  Modeling of nonlinear thermal resistance in FinFETs , 2016 .

[10]  Kenneth E. Goodson,et al.  THERMAL CONDUCTION IN SILICON MICRO- AND NANOSTRUCTURES , 2005 .

[11]  Tsunaki Takahashi,et al.  Self-Heating Effects and Analog Performance Optimization of Fin-Type Field-Effect Transistors , 2013 .

[12]  Hai Jiang,et al.  A novel synthesis of Rent's rule and effective-media theory predicts FEOL and BEOL reliability of self-heated ICs , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[13]  Chris Auth,et al.  22-nm fully-depleted tri-gate CMOS transistors , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

[14]  Dick James,et al.  Intel Ivy Bridge unveiled — The first commercial tri-gate, high-k, metal-gate CPU , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

[15]  O. Semenov,et al.  Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits , 2006, IEEE Transactions on Device and Materials Reliability.

[16]  J. Jeon,et al.  Highly Strained Si pFinFET on SiC With Good Control of Sub-Fin Leakage and Self-Heating , 2014, IEEE Electron Device Letters.

[17]  Eric Pop,et al.  Heat Generation and Transport in Nanometer-Scale Transistors , 2006, Proceedings of the IEEE.

[18]  C. Liu,et al.  Thermal resistance modeling of back-end interconnect and intrinsic FinFETs, and transient simulation of inverters with capacitive loading effects , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).