A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme

A 0.8 V/100 MHz/sub-5 mW-operated 1-Mbit SRAM cell architecture which uses a charge-recycle offset-source driving (OSD) scheme, is proposed. This paper is focused on why OSD can reduce the power dissipation to /spl les/1/14 compared to the previously reported negative source drive (NSD) scheme, while achieving a 0.8 V/100 MHz operation. OSD features as follows: (1) "parallel shift" of the potential of storage-node pairs V/sub H//V/sub L/ (0.8 V/0 V->1.4 V/0.6 V) for the unselected cell, (2) source line over-drive (0.6 V->0 V) when accessing the cell, (3) column-decoded source line drive in wordline (WL) direction, enabling to realize a pseudo cross-point access, and (4) charge-recycling source line drive, making it possible to eliminate the power-loss when resetting the potential of source line (0 V->0.6 V). OSD no longer requires negative-bias (-0.6 V) pumping circuit which has an intolerable-low supply-efficiency at 0.8 V Vcc, necessary to realize the source over-driving, unlike NSD. Thus, OSD can be exploited to realize 75% over-driving of source line (V/sub Gs/=0.8 V->1.4 V) necessary to achieve 100 MHz-operation, without an intolerable power-loss, instead of NSD. To demonstrate the effectiveness of OSD, power consumption comparisons were made between this work and NSD. For all measurements, the same access time conditions were used based on the simulated and measured data of the 0.35 /spl mu/m 1 Mbit-CMOS SRAM (16 K-word/spl times/64-bit). OSD enables a dramatic power reduction of over 93%, while maintaining 100 MHz operation even at 0.8 V Vcc, compared to NSD.