An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures

Circuit-switched networks provide guaranteed transmission latency and throughput, and hence are suitable for many network-on-chip (NoC) architectures requiring quality-of-service. A circuit-switched on-chip network needs a scheduler to arrange communication paths and allocate a proper bandwidth for each path. Such a scheduler offers an effective solution for a critical step in the NoC design. In this paper, we propose an efficient scheduler for pre-scheduled circuit-switched on-chip networks. Based on simulations, we show that low delivery latency for circuit-switched on-chip networks can be achieved with our scheduler. Furthermore, with efficient scheduling, the cost of the switches can be also minimized

[1]  Chia-Ming Wu,et al.  Mapping of IP cores to network-on-chip architectures based on communication task graphs , 2005, 2005 6th International Conference on ASIC.

[2]  William J. Dally,et al.  Guaranteed scheduling for switches with configuration overhead , 2003, IEEE/ACM Trans. Netw..

[3]  Drew Wingard.  MicroNetwork-based integration for SOCs , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[4]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[5]  R. Marculescu,et al.  Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Clifford Stein,et al.  Introduction to Algorithms, 2nd edition. , 2001 .

[7]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[8]  Alberto L. Sangiovanni-Vincentelli,et al.  Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[10]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[11]  Hannu Tenhunen,et al.  A guaranteed-throughput switch for network-on-chip , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

[12]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[13]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[14]  Dake Liu,et al.  SoCBUS: switched network on chip for hard real time embedded systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[15]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[16]  Shashi Kumar,et al.  A two-step genetic algorithm for mapping task graphs to a network on chip architecture , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[17]  T. Inukai,et al.  An Efficient SS/TDMA Time Slot Assignment Algorithm , 1979, IEEE Trans. Commun..

[18]  Chia-Ming Wu,et al.  Efficient Switches for Network-on-Chip Based Embedded Systems , 2005, EUC.

[19]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.