A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

A formal semantic analysis for Verilog-HDL and VHDL is provided in order to give the simulation model especially focusing on signal scheduling and timing control mechanism. Our semantics is faithful to LRM and is expected to become a coherent first step for a future semantic interoperability analysis on multisemantic-domain such as Verilog-ARMS and VHDL-AMS. By ignoring the differences of the two simulation cycles, we can use the common semantic functions and the common simulation cycle.

[1]  Egon Brger,et al.  Formal de nition of an abstract VHDL''''93 simulator by EA - machines , 1995 .

[2]  Serafín Olcoz.  A Formal Model of VHDL Using Coloured Petri Nets , 1995 .

[3]  Carlos Delgado Kloos,et al.  A semantic model for VHDL-AMS , 1997, CHARME.

[4]  Tom J. Kazmierski.  A formal description of VHDL-AMS analogue systems , 1998, Proceedings Design, Automation and Test in Europe.

[5]  C. E. Cummings.  Verilog nonblocking assignments demystified , 1998, Proceedings International Verilog HDL Conference and VHDL International Users Forum.

[6]  Dominique Borrione,et al.  An approach to Verilog-VHDL interoperability for synchronous designs , 1997, CHARME.

[7]  Uwe Glässer,et al.  Abstract State Machine Semantics of SDL , 1997, J. Univers. Comput. Sci..

[8]  Thomas Kropf,et al.  A Flow Graph Semantics of VHDL: A Basis for Hardware Verification with VHDL , 1995 .

[9]  Ieee Standards Board.  IEEE Standard hardware Description language : based on the Verilog hardware description language , 1996 .

[10]  Carlos Delgado Kloos,et al.  Formal Semantics for VHDL , 1995 .

[11]  Douglas J. Smith,et al.  VHDL & Verilog compared & contrasted—plus modeled example written in VHDL, Verilog and C , 1996, DAC '96.

[12]  尚 佐々木,et al.  Semantic Analysis of VHDL - AMS by Attribute Grammar , 1997 .

[13]  Hisashi Sasaki,et al.  Semantic Validation of VHDL-AMS by an Abstract State Machine , 1997 .

[14]  Michael J. C. Gordon,et al.  The semantic challenge of Verilog HDL , 1995, Proceedings of Tenth Annual IEEE Symposium on Logic in Computer Science.

[15]  Gregory D. Peterson,et al.  The advanced intermediate representation with extensibility/common environment (AIRE/CE) , 1998, Proceedings of the IEEE 1998 National Aerospace and Electronics Conference. NAECON 1998. Celebrating 50 Years (Cat. No.98CH36185).

[16]  V. Berman.  Standard Verilog-VHDL interoperability , 1994, International Verilog HDL Conference.

[17]  Jacques Rouillard,et al.  Verilog and VHDL , 1992 .