A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit

This paper describes a fourth generation Intel Pentium 4 processor integer execution core operating at 9 GHz in a 1.3-V, 65-nm CMOS technology at 70degC. Low-voltage-swing circuits of the 90-nm design are replaced by: 1) 2times frequency fast clock (FCLK)-optimized domino clocking scheme; 2) segmented arithmetic and logic unit (ALU) front-end multiplexer; 3) sparse-tree ALU adder; 4) merged add/subtract sparse-tree address generation unit (AGU) design; 5) speculative RC-delay-optimized rotator; and 6) single-rail L0 cache and alignment multiplexer, resulting in 8.4% reduction in integer core normalized active power and 42% reduction in normalized leakage power. The use of standard domino/static tools and methodologies lowers design complexity, reducing development cost and time. The redesign also reduces integer core thermal density, resulting in an 8degC reduction in CPU operating temperature

[1]  P. Bai,et al.  A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[2]  R. Krishnamurthy,et al.  A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[3]  C. Webb,et al.  A scalable X86 CPU design for 90 nm process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[4]  S. Wijeratne,et al.  Low-voltage-swing logic circuits for a 7GHz x86 integer core , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).