论文信息 - Sub-threshold SRAM bit cell pnn for VDDmin and power reduction

Sub-threshold SRAM bit cell pnn for VDDmin and power reduction

The bit cell is a key component that determines the VDD min and power consumption of a sub-threshold static random access memory (SRAM). A new bit cell with a pnn -type latch structure is proposed. The analysis and measurement results indicate that the pnn bit cell outperforms the conventional bit cells in terms of VDD min and power reduction.

Jinn-Shyan Wang | Y. C. Chien | I. H. Chiang

[1] Shi-Yu Huang,et al. P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation , 2011, IEEE Journal of Solid-State Circuits.

[2] Wei Hwang,et al. Design and Iso-Area $V_{\min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3] Kaushik Roy,et al. A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[4] R.H. Dennard,et al. An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.

[5] Chien-Yu Lu,et al. A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing , 2012, IEEE Journal of Solid-State Circuits.