Reliable Low-Power Multiplier Design using Fixed-Width Replica Redundancy Block

In this paper, proposed An Area Efficient Multiplier De-sign Using Fixed-Width Replica Redundancy by adopting algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier to build the reduced precision replica redundancy block (RPR). The proposed ANT architecture can meet the demand of high precision, low power consumption, and area efficiency. We design the fixed-width RPR with error compensation circuit via analysing of probability and statistics. Using the partial product terms of input correction vector and minor in-put correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simplified. In a 16 × 16 bit ANT multiplier, circuit area in our fixed-width RPR can be lower and power consumption in our ANT design can be saved as com-pared with the state-of-art ANT design.