Development of control circuits for the CCD stereo camera of Chang'E-1 satellite based on FPGA

The CCD Stereo Camera is a principal science payload on board the Chang'E-1 (CE-1) satellite, developed and launched by China for the first Lunar Exploration Program. The principal task of the camera is to take image of the lunar surface in the visible band and obtains three-dimensional lunar terrain. The CCD Stereo Camera is designed based on threelinear array photogrammetric theories. The focal plane of the camera is comprised of a frame transfer CCD with size of 1024x1024 pixels. There are only three lines to be used to form a three-linear array, and the other lines are not used. The timing and control circuits of the camera are designed based on FPGA. An Actel's anti-fuse based FPGA, A1020B, is available, but the speed and logical resources of the device both are limited. This paper describes the design requirements, considerations and trade-off subject to the constraints. Especially, A novel logic circuit is introduced to generate the pulses with width of about 10ns~20ns with constraint of 8MHz external clock, which is used to design correlated double sampling (CDS) control signals and CCD reset signal. Finally, the result of flying verifications on-board of the timing and control circuits are also described.