Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems

Cache reconfiguration is a promising optimization technique for reducing memory hierarchy energy consumption with little or no impact on overall system performance. While cache reconfiguration is successful in desktop-based systems, it is not directly applicable in real-time systems due to timing constraints. Existing scheduling-aware cache reconfiguration techniques consider only one-level cache. It is a major challenge to dynamically tune multi-level caches since the exploration space is prohibitively large. This paper efficiently integrates cache reconfiguration in soft real-time systems with a unified two-level cache hierarchy. We utilize a set of exploration heuristics during our static analysis which effectively decreases the exploration time while keeps the generated profile results beneficial to be leveraged during runtime. Our experimental results have demonstrated 32 - 49% energy savings with minor impact on performance.

[1]  Frank Vahid,et al.  A self-tuning cache architecture for embedded systems , 2004 .

[2]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[3]  Bill Moyer,et al.  A low power unified cache architecture providing power and performance flexibility , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[4]  Nikil D. Dutt,et al.  Automatic tuning of two-level caches to embedded applications , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[5]  Yudong Tan,et al.  Timing analysis for preemptive multi-tasking real-time systems with caches , 2004 .

[6]  Isabelle Puaut,et al.  Low-complexity algorithms for static cache locking in multitasking hard real-time systems , 2002, 23rd IEEE Real-Time Systems Symposium, 2002. RTSS 2002..

[7]  Brad Calder,et al.  Discovering and Exploiting Program Phases , 2003, IEEE Micro.

[8]  Andrew Wolfe,et al.  Software-based cache partitioning for real-time applications , 1994 .

[9]  Nikil D. Dutt,et al.  Fast Configurable-Cache Tuning With a Unified Second-Level Cache , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Ann Gordon-Ross,et al.  SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems , 2009, 2009 22nd International Conference on VLSI Design.

[11]  Mehdi Modarressi,et al.  A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems , 2006, 2006 Canadian Conference on Electrical and Computer Engineering.

[12]  Antonio González,et al.  A dynamically reconfigurable cache for multithreaded processors , 2006, J. Embed. Comput..

[13]  Jane W.-S. Liu.  Real-Time Systems , 2000, Encyclopedia of Algorithms.

[14]  David H. Albonesi,et al.  Selective cache ways: on-demand cache resource allocation , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.