A fully integrated RSSI and an ultra-low power SAR ADC for 5.8 GHz DSRC ETC transceiver

Abstract This study presents a monolithic received signal strength indicator (RSSI) and an ultra-low power SAR ADC for 5.8 GHz DSRC transceiver in China electronic toll collection systems. In order to meet the stringent requirement of wide input range for the transceiver, two RSSIs collaborate with auxiliary ADC circuits to provide the digitalized received signal strength to the digital baseband of a transceiver. The RSSI design achieves fast transient response and low power consumption with a small die area by using internal active low-pass filters instead of external passive ones. The proposed design has been fabricated using a 0.13 µm 2P6M CMOS technology. Measurement results show that the overall input dynamic range is 86 dB with an accuracy of  ±1.72 dB and a transient response of less than 2 µs. Compared with the state-of-the-art designs in the literature, the overall input range and transient settling time are improved by at least 14.6%, and 300%, respectively.

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