Stability and accuracy analysis of power hardware in the loop system with different interface algorithms

The power hardware in the loop (PHIL) technology allows for testing a physical device under test (DUT) connected to the real time simulated rest of system (ROS) through a power electronic interface and interface algorithm (IA). Stability and accuracy questions remain open due to the non-ideal interface converter. This paper presents a frequency-domain stability analysis and a time-domain accuracy analysis of the PHIL system with different IAs, taking into account of the delay factors in the PHIL system. Results show that the damping impedance method (DIM) IA can realize a perfectly stable PHIL system, while the ideal transformer model (ITM) IA needs be modified to stabilize the PHIL system. The voltage and current expressions at both ROS side and DUT side are derived to make considerations about the accuracy of the PHIL system. Results show that matching of the waveforms at ROS and DUT sides can be achieved for passive DUTs with the DIM IA; however, for active DUTs, the matching suffers from the delay factors.

[1]  Felix Lehfuss,et al.  The Limitations of Digital Simulation and the Advantages of PHIL Testing in Studying Distributed Generation Provision of Ancillary Services , 2015, IEEE Transactions on Industrial Electronics.

[2]  C. S. Edrington,et al.  Improved power hardware in the loop interface methods via impedance matching , 2013, 2013 IEEE Electric Ship Technologies Symposium (ESTS).

[3]  A. Monti,et al.  Interface issues in hardware-in-the-loop simulation , 2005, IEEE Electric Ship Technologies Symposium, 2005..

[4]  K. R. Padiyar,et al.  Analysis and performance evaluation of a distribution STATCOM for compensating voltage fluctuations , 2001 .

[5]  Enrico Santi,et al.  Stability and accuracy considerations in the design and implementation of a kilowatt-scale DC power hardware-in-the-loop platform , 2014, 2014 IEEE Energy Conversion Congress and Exposition (ECCE).

[6]  Enrico Santi,et al.  Improved power hardware-in-the-loop interface algorithm using wideband system identification , 2014, 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014.

[7]  A. Monti,et al.  Hardware-in-the-loop testing of digital power controllers , 2006, Twenty-First Annual IEEE Applied Power Electronics Conference and Exposition, 2006. APEC '06..

[8]  S. Kazemlou,et al.  Stability of multi-generator power system with penetration of renewable energy sources , 2012, 2012 IEEE Power and Energy Society General Meeting.

[9]  Michael Steurer,et al.  A Megawatt-Scale Power Hardware-in-the-Loop Simulation Setup for Motor Drives , 2010, IEEE Transactions on Industrial Electronics.

[10]  Alexander Viehweider,et al.  Power hardware in the loop simulation with feedback current filtering for electric systems , 2011, IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society.

[11]  G. Sybille,et al.  Modeling and simulation of a distribution STATCOM using Simulink's Power System Blockset , 2001, IECON'01. 27th Annual Conference of the IEEE Industrial Electronics Society (Cat. No.37243).

[12]  Thomas Baldwin,et al.  Simulation by Selecting Appropriate Interface Algorithms , 2007 .

[13]  T. Strasser,et al.  Implementation of a multi-rating interface for Power-Hardware-in-the-Loop simulations , 2012, IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society.

[14]  Arindam Ghosh,et al.  Load compensating DSTATCOM in weak AC systems , 2003 .