Circuit design issues in multi-gate FET CMOS technologies

Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V

[1]  A. Marshall,et al.  ESD evaluation of the emerging MuGFET technology , 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

[2]  R. Rooyackers,et al.  A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node , 2004, IEEE Electron Device Letters.

[3]  G. Knoblinger,et al.  Design and evaluation of basic analog circuits in an emerging MuGFET technology , 2005, 2005 IEEE International SOI Conference Proceedings.

[4]  S. Hareland,et al.  Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[5]  J.-P. Colinge,et al.  Novel gate concepts for MOS devices , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

[6]  J. Bokor,et al.  FinFET-a quasi-planar double-gate MOSFET , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).