Delta-I Noise Scaling in Sub-Micron CMOS Technologies

Delta-I or switching noise is becoming an important design constraint in today's digital and mixed signal ICs. In this work a detailed analysis of the scaling of the switching noise is performed based on current technologies and two different scaling scenarios: high performance driven scaling and low power driven scaling. The results were obtained by simulating a test structure using Hspice and LEVEL3 models for the transistors.