This paper presents a generalized strategy for optimal design of on-line integrated fault detector for linear analog systems. The method consists in processing the available node voltage signals to provide a residual signal that carries information about the faults. Contrary to previously proposed techniques dealing only with the particular case of state variable systems, the use of extra circuitry with the objective of concurrent fault detection is extended here without limitation to a larger class of linear analog systems for which the state variables do not necessary need to be available as measurable voltages. This requires the use of an extended state space model for any linear analog system. For this purpose, an algorithm providing the extended state space model from a netlist description is developed and implemented.
[1]
Suku Nair,et al.
Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays
,
1990,
IEEE Trans. Computers.
[2]
Paul M. Frank,et al.
Fault diagnosis in dynamic systems using analytical and knowledge-based redundancy: A survey and some new results
,
1990,
Autom..
[3]
Jacob A. Abraham,et al.
Fault-Tolerant FFT Networks
,
1988,
IEEE Trans. Computers.
[4]
Abhijit Chatterjee,et al.
Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums
,
1993,
IEEE Trans. Very Large Scale Integr. Syst..