Implementation Topology of Full Adder Cells
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[1] M. A. Karim,et al. BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control , 2012, IEEE Transactions on Electron Devices.
[2] Ali M. Niknejad,et al. BSIM—SPICE Models Enable FinFET and UTB IC Designs , 2013, IEEE Access.
[3] Vinay Kumar,et al. Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[4] Tarek Darwish,et al. Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[5] Wolfgang Fichtner,et al. Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.
[6] Haomin Wu,et al. A new design of the CMOS full adder , 1992 .
[7] Massimo Alioto,et al. Analysis and comparison on full adder block in submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[8] Omid Kavehei,et al. A novel low-power full-adder cell for low voltage , 2009, Integr..
[9] Pankaj Kumar,et al. Low voltage high performance hybrid full adder , 2016 .
[10] Xunwei Wu,et al. Design of ternary CMOS circuits based on transmission function theory , 1988 .