An efficient architecture of deblocking filter with high frame rate for H.264/AVC

In this paper, we propose an efficient hardware architecture of the deblocking filter for H.264/JVT/AVC. Earlier designs have demerit of long processing time, since the reading, writing and filtering operations have been processed in each cycles. This paper proposes a new architecture that enables filtering of vertical edge concurrent with data loading as well as filtering of horizontal edge concurrent with writing to the external memory. The experimental result shows that the necessary cycle for filtering can be reduced by 38% in comparison with the conventional method and the new architecture has advantage in power consumption.