Modelling and Veriflcation of Delay-Insensitive Circuits using CCS and the

The modelling of delay-insensitive asynchronous circuits in the process calculus CCS is addressed. MUST-testing (rather than bisimulation) is found to support veriflcation both of the property of delay-insensitivity and of design by stepwise reflnement. Automated veriflcation is possible with a well-known tool, the Edinburgh Concurrency Workbench.

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