A 1.2V 64fJ/conversion-step continuous-time ΣΔ modulator using asynchronous SAR quantizer and digital ΣΔ truncator

A 3rd-order single-loop continuous time sigma-delta modulator (CTSDM) with 6-bit asynchronous SAR quantizer and digital delta-sigma truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed asynchronous SAR based quantizer reduces the area and power dramatically with the help of digital truncation technique. In addition, the modulator incorporating the proposed operational amplifiers (op-amp) with ac coupled push-pull stage is to improve the high frequency driving capability. The modulator sampling at 65MHz achieves 83.4dB dynamic range (DR) and 80/79.6dB peak SNR/SNDR with 1.92MHz bandwidth (BW) in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Implemented in 40nm CMOS, the modulator occupies 0.051mm2 and consumes 1.91mW from a 1.2V supply. A 64fJ/conversion figure of merit (FOM) is achieved.

[1]  F. Kuttner,et al.  A 3mW 74dB SNR 2MHz CT /spl Delta//spl Sigma/ ADC with a tracking-ADC-quantizer in 0.13 /spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[2]  Mohammad Ranjbar,et al.  A 3.1 mW Continuous-Time ΔΣ Modulator With 5-Bit Successive Approximation Quantizer for WCDMA , 2010, IEEE Journal of Solid-State Circuits.

[3]  José B. Silva,et al.  A 2.8 mW ΔΣ ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[4]  Yung-Yu Lin,et al.  A 1.2V 2MHz BW 0.084mm2 CT ΔΣ ADC with −97.7dBc THD and 80dB DR using low-latency DEM , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  W. Sansen,et al.  A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC , 2000, IEEE Journal of Solid-State Circuits.

[6]  Franco Maloberti,et al.  A low-power mMultibiit ΣΔ modulator in 90-nm digital CMOS without DEM , 2005 .

[7]  F. Maloberti,et al.  A low-power multi-bit /spl Delta//spl Sigma/ modulator in 90nm digital CMOS without DEM , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[8]  Koji Obata,et al.  A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver , 2010, IEEE Custom Integrated Circuits Conference 2010.

[9]  Robert H. M. van Veldhoven,et al.  An Inverter-Based Hybrid ΔΣ Modulator , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[10]  Chung-Ming Huang,et al.  A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).