Runtime adaptive multi-processor system-on-chip: RAMPSoC

Current trends in high performance computing show, that the usage of multiprocessor systems on chip are one approach for the requirements of computing intensive applications. The multiprocessor system on chip (MPSoC) approaches often provide a static and homogeneous infrastructure of networked microprocessor on the chip die. A novel idea in this research area is to introduce the dynamic adaptivity of reconfigurable hardware in order to provide a flexible heterogeneous set of processing elements during run-time. This extension of the MPSoC idea by introducing run-time reconfiguration delivers a new degree of freedom for system design as well as for the optimized distribution of computing tasks to the adapted processing cells on the architecture related to the changing application requirements. The "computing in time and space"paradigm and the extension with the new degree of freedom for MPSoCs will be presented with the RAMPSoC approach described in this paper.

[1]  George Bosilca,et al.  Open MPI: Goals, Concept, and Design of a Next Generation MPI Implementation , 2004, PVM/MPI.

[2]  Norbert Wehn,et al.  A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding , 2006, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation.

[3]  Azzedine Boukerche,et al.  A parallel strategy for biological sequence alignment in restricted memory space , 2008, J. Parallel Distributed Comput..

[4]  Jürgen Becker,et al.  Configware and morphware going mainstream , 2003, J. Syst. Archit..

[5]  Jürgen Becker,et al.  New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[6]  George Bosilca,et al.  Open MPI: A High-Performance, Heterogeneous MPI , 2006, 2006 IEEE International Conference on Cluster Computing.

[7]  Bin Liu,et al.  Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[8]  Message Passing Interface Forum.  MPI: A message - passing interface standard , 1994 .

[9]  Axel Jantsch,et al.  Networks on chip , 2003 .

[10]  Paul Chow,et al.  TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[11]  I. Xilinx.  Virtex series configuration architecture user guide , 2000 .

[12]  Bernard Pottier,et al.  Co-Design of Massively Parallel Embedded Processor Architectures , 2005, ReCoSoC.

[13]  Lars Braun,et al.  Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[14]  M. Coppola,et al.  Spidergon: a novel on-chip communication network , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..

[15]  Jürgen Becker,et al.  A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

[16]  Jürgen Becker,et al.  High performance reconfigurable multi-processor-based computing on FPGAs , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

[17]  Jürgen Becker,et al.  CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

[18]  Rudy Lauwereins,et al.  Reconfigurable Instruction Set Processors from a Hardware/Software Perspective , 2002, IEEE Trans. Software Eng..

[19]  Wayne H. Wolf,et al.  The future of multiprocessor systems-on-chips , 2004, Proceedings. 41st Design Automation Conference, 2004..

[20]  Hans-Peter Rosinger.  Connecting Customized IP to the MicroBlaze Soft Processor Using the Fast Simplex Link ( FSL ) Channel , 2003 .

[21]  David Pellerin,et al.  Practical FPGA programming in C , 2005 .

[22]  Christophe Bobda,et al.  SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

[23]  William Gropp,et al.  Skjellum using mpi: portable parallel programming with the message-passing interface , 1994 .

[24]  Muhammad Shafique,et al.  RISPP: Rotating Instruction Set Processing Platform , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[25]  Jürgen Becker,et al.  Realization of Real-Time Control Flow Oriented Automotive Applications on a Soft-core Multiprocessor System based on Xilinx Virtex II FPGAs , 2005 .

[26]  Timothy Mattson,et al.  A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).